2. Immediate Addressing

2. Immediate Addressing

• The operand is a constant within the instruction itself in immediate addressing.
• Immediate addressing is similar to register addressing, the instructions will be executed quickly because they avoid the delays associated with memory access.
• Since the destination of the jump instruction format is held in the instruction, so it can also be considered an example of immediate addressing.

1. Register Modes

1. Register Modes

• Register addressing is the simplest addressing mode.
• Both operands are in a register.Instructions will be executed quickly because they avoid the delays associated with memory access.
• The number of registers is limited since only a few bits are reserved to select a register.
• It takes n bits to address 2ⁿ registers, which can fit in five bits since there are 32 registers.
  

Addressing Modes

Addressing Modes

MIPS has only a small number of ways that is computes addresses in memory. The address can be an address of an instruction (for branch and jump instructions) or it can be an address of data (for load and store instructions).

For any given operation, such as load, add or branch, there are often many different ways to specify the address of the operand(s).
The different ways of determining the address are called addressing modes.

We will look at the 4 ways addresses are computed

1. Register Addressing
2. Immediate Addressing
3. PC-Relative Addressing
4. Base Addressing

Associative Caches

Associative Caches

-Increased associativity decrease miss rate but with diminishing returns


Spectrum of associativity

Type of associative

1. Fully Associative
--In a fully associative scheme, any slot can store the cache line. The hardware for finding whether the desired data is in the cache requires comparing the tag bits of the address to the tag bits of every slot (in parallel), and making sure the valid bit is set.

2. Set associative
--A set-associative cache scheme is a combination of fully associative and direct mapped schemes. You group slots into sets. You find the appropriate set for a given address (which is like the direct mapped scheme), and within the set you find the appropriate slot (which is like the fully associative scheme).

Example

--Compare 4-blocks caches with block access sequence: 0,8,0,6,8

Cache Performance

Cache Performance

• There are 3 formula need to memorize:

1. Memory stall cycles

2. CPU time
= (CPU execution cycles + Memory stall cycles) x Cycle time

3. Average memory access time (AMAT)

= Hit time + (Miss rate x Miss penalty)

More Cache Performance Formula

n

nCan split access time into instructions & data:

pAverage. memory. access. time =
(% instruction accesses) × (instruction. memory. access time) + (% data accesses) × (data memory. access time)

nAnother simple formula:

pCPU time = (CPU execution clock cycles + Memory stall clock cycles) × cycle time

nCan break stalls into reads and writes:

pMemory stall cycles =
(Reads × read miss rate × read miss penalty) + (Writes × write miss rate × write miss penalty)

Performance Summary

1. Improving Cache Performance

2. The organization of a memory system affects its  performance.

--The cache size, block size, and associativity affect the miss rate.

--We can organize the main memory to help reduce miss penalties. For example, interleaved memory supports pipelined data accesses.

3.Can’t neglect cache behavior when evaluating system performance

Instruction Type Application

Instruction Type Application

a)

Instruction type : Non-Jump, R-type

Type                : R Type

Example           : add rd,rs,rt 

ALU Usage      :  1. PC update : No update beyond the normal increment.
                           2. Source operand fetch : source are rs and rt
                           3. ALU operation : Determined by the function ( fn ) field
                           4. Memory access : None
                           5. Register write : The result from the ALU is written to rd .

b)

Instruction type : Jump Register, R-type

Type                : R Type

Example           : jalr rd,rs 

ALU Usage      :  1. PC update : No update beyond the normal increment.
                           2. Source operand fetch :source are rs and rt
                           3. ALU operation : Determined by the function field
                           4. Memory access : None
                           5. Register write : The result from the ALU is written to rd .

c)

Instruction type : Immediate

Type                :  I Type

Example           : addi rt,rs,imn

ALU Usage      : 1. PC update : No update beyond the normal increment.
                          2. Source operand fetch : Source are rs and immediate field. For all instructions except sltiu                           ,the immediate field is sign extended . For sltiu , the immediate field is zero extended .
                         3. ALU operation : Determined by the opcode
                         4. Memory access : None.
                         5. Register write : The result from the ALU is written to rt .

d)

Instruction type : Branch

Type                :  I Type

Example           : beq $rs,$rt, imm

ALU Usage      : 1. PC update : If the branch condition is true , PC--PC + 4 + ( signed-extended immediate                              field ) << 2 .
                          2. Source operand fetch : Source are rs and rt
                          3. ALU operation : The source operands are subtracted for comparison .
                          4. Memory access : None.
                          5. Register write : None.

e)

Instruction type : Load

Type                :  I Type

Example           : Iw rt, imm(rs)

ALU Usage      : 1. PC update : No update beyond the normal increment
                          2. Source operand fetch : Source are rs and the sign extended immediate field
                          3. ALU operation : The two source operands are added to get the memory address .
                          4. Memory access : A memory read control signal is sent to memory . The result from the                                ALU is sent to memory as the address .
                          5. Register write : The data from memory is written to rt .

f)

Instruction type : Store

Type                :  I Type

Example           : sw rt,imm(rs)

ALU Usage      : 1. PC update : No update beyond the normal increment

                          2. Source operand fetch : Source are rs and the sign extended immediate field. rt register                                   also fetched.

                          3. ALU operation : Two source operand are added to get he memory address.

                          4. Memory access : A memory write control signal is sent to memory. The result is sent to                                 memory as the address. Content of rt are sent to memory as the write data.

                          5. Register write : None.

g) 

Instruction type : Register Jump

Type                :  R Type

Example           : beq $rs.$rt, imm

ALU Usage      : 1. PC update : jr and jalr    PC <-- rs

                          2. Source operand fetch : Only rs register.

                          3. ALU operation : None.

                          4. Memory access : None.

                          5. Register write : jr :     There is no register write                 

                                                      jalr :   rd<-- PC + 4

                           *For jalr, the incremented PC value must be capture the target address is placed into the                                PC. With edge-triggered clocking this is easy to do. There is an adder to produce the                                    PC+4 values. The PC does not change until the start of the next cycle, adder output will                                no change until the start of the next cycle.

h)

Instruction type : Non-Register Jump

Type                :  R Type

Example           :  jal target

ALU Usage      : 1. PC update : jr and jalr   PC <-- target address

                           * The target address is the concatenation of the high order 4 bits of PC+ . The target field                                 of the instruction and two 0 bits.

                          2. Source operand fetch : None

                          3. ALU opration : None.

                              Memory access : None

                              jr : There is no register write.

                              jal : ra <-- PC +4

                            *For jalr, the incremented PC value must be capture the target address is placed into the                                PC. With edge-triggered clocking this is easy to do. There is an adder to produce the                                    PC+4 values. The PC does not change until the start of the next cycle, adder output will                                no change until the start of the next cycle.

MIPS (Introduction/ Register Type/Immediate Type/Jump Type)

MIPS

The MIPS architecture (which originally stood for “Microprocessor without Interlocked Pipeline Stages”) is a little endian, word addressable, three-address, fixed-length ISA. This is a load and store architecture, which means only the load and store instructions can access memory. All other instructions must use registers for operands, which implies that this ISA needs a large register set. MIPS is also limited to fixed-length operations (those that operate on data with the same number of bytes).

The MIPS instructions had up to four fields: an opcode, two
operand addresses, and one result address. Essentially three instruction formats are available: the I type (immediate), the R type (register), and the J type (jump). R type instructions have a 6-bit opcode, a 5-bit source register, a 5-bit target register, a 5-bit shift amount, and a 6-bit function. I type instructions have a 6-bit operand, a 5-bit source register, a 5-bit target register or branch condition, and a 16-bit immediate branch displacement or address displacement. J type instructions have a 6-bit opcode and a 26-bit target address.


Instruction format

An instruction is normally made up of a combination of an operation code and some way of specifying an operand,most commonly by its location or address in memory.




There are 3 types of instruction format

• Register Type (R-type) 
• Immediate Type (I-type) 
• Jump Type (J-type) 

Register Type (R-type)



Opcode : Machine code representation of instruction mnemonic. The opcode field is 6 bits long ( bit 26 to                     bit 31)

rs,rt,rd : The numeric representations of the source registers and the destination register. These numbers
             correspond to the $X representation of a register, such as $0 or $31. Each of these fields is 5 bits                  long. (25 to 21, 20 to 16, and 15 to 11, respectively).

Shamt : Used with the shift and rotate instructions, this is the amount by which the source operand rs is
             rotated/shifted. This field is 5 bits long (6 to 10).

Funct : For instructions that share an opcode, the funct parameter contains the necessary control codes to
           differentiate the different instructions. 6 bits long (0 to 5).



Immediate Type (I-type)



Opcode : The 6-bit opcode of the instruction. In I instructions, all mneumonics have a one-to-one                                 correspondence with the underlying opcodes. This is because there is no funct parameter to                           differentiate instructions with an identical opcode. 6 bits (26 to 31).

rs,rt : The source and destination register operands, respectively. 5 bits each (21 to 25 and 16 to 20,                       respectively).



Jump Type (J-type)


Opcode : The 6 bit opcode corresponding to the particular jump command. (26 to 31).


Target (address) : A 26-bit address of the destination. (0 to 25).