MIPS (Introduction/ Register Type/Immediate Type/Jump Type)

MIPS

The MIPS architecture (which originally stood for “Microprocessor without Interlocked Pipeline Stages”) is a little endian, word addressable, three-address, fixed-length ISA. This is a load and store architecture, which means only the load and store instructions can access memory. All other instructions must use registers for operands, which implies that this ISA needs a large register set. MIPS is also limited to fixed-length operations (those that operate on data with the same number of bytes).

The MIPS instructions had up to four fields: an opcode, two
operand addresses, and one result address. Essentially three instruction formats are available: the I type (immediate), the R type (register), and the J type (jump). R type instructions have a 6-bit opcode, a 5-bit source register, a 5-bit target register, a 5-bit shift amount, and a 6-bit function. I type instructions have a 6-bit operand, a 5-bit source register, a 5-bit target register or branch condition, and a 16-bit immediate branch displacement or address displacement. J type instructions have a 6-bit opcode and a 26-bit target address.


Instruction format

An instruction is normally made up of a combination of an operation code and some way of specifying an operand,most commonly by its location or address in memory.




There are 3 types of instruction format

• Register Type (R-type) 
• Immediate Type (I-type) 
• Jump Type (J-type) 

Register Type (R-type)



Opcode : Machine code representation of instruction mnemonic. The opcode field is 6 bits long ( bit 26 to                     bit 31)

rs,rt,rd : The numeric representations of the source registers and the destination register. These numbers
             correspond to the $X representation of a register, such as $0 or $31. Each of these fields is 5 bits                  long. (25 to 21, 20 to 16, and 15 to 11, respectively).

Shamt : Used with the shift and rotate instructions, this is the amount by which the source operand rs is
             rotated/shifted. This field is 5 bits long (6 to 10).

Funct : For instructions that share an opcode, the funct parameter contains the necessary control codes to
           differentiate the different instructions. 6 bits long (0 to 5).



Immediate Type (I-type)



Opcode : The 6-bit opcode of the instruction. In I instructions, all mneumonics have a one-to-one                                 correspondence with the underlying opcodes. This is because there is no funct parameter to                           differentiate instructions with an identical opcode. 6 bits (26 to 31).

rs,rt : The source and destination register operands, respectively. 5 bits each (21 to 25 and 16 to 20,                       respectively).



Jump Type (J-type)


Opcode : The 6 bit opcode corresponding to the particular jump command. (26 to 31).


Target (address) : A 26-bit address of the destination. (0 to 25).